In MRAM memory devices, current drivers are used to pass pre-determined current levels to selected rows and columns. As shown in FIG. 1, a typical implementation may include a pair of word line current drivers. Specifically, a word line current driver 11 of the pair of current drivers is shown on left and another word line current driver 12 of the pair of current drivers is shown on right of the FIG. 1. One pair of such word line current drivers is used for each word line as shown in FIG. 1. Further, a bit line current driver 13 is used on top and another bit line current driver 14 is used at bottom, as shown in FIG. 1. Specifically, a pair of such bit line current drivers is used for each bit line as shown in FIG. 1.
Various circuits may be designed to realize the aforementioned currents drivers 11-14. By way of example, FIG. 2, a transistor circuit 21 is used to realize the current drivers 11-14. In operation, for logic level ‘1’, an “Enable” signal is activated to turn off transistors M1 and M5. Further, when a reference current source ‘Iref’ is generated, transistor M4 is turned on and current is mirrored from transistor M2 to transistor M3. In one embodiment, when Iref=100 uA and a size ratio of (W/L)M3/(W/L)M2=10, then M3 can supply current of 1 mA (100 uA×10=1 mA). In the same way, M3 can supply current of 10 mA, when M3 to M2 size ratio is 100 and Iref=100 uA. The concept of current mirroring, where M3 can provide current equal to Iref multiplied by size ratio of M3 and M2, is known in the art. Keeping Iref constant, the need for M3 to deliver large currents during write operations in a MRAM memory requires the M3 size to be large. However, M3 has to be drawn in a layout to fit in relatively small pitch of a memory bit cell, and a large M3 size adversely affects total die size.
In an MRAM array, since only one row or column in each memory block needs to pass current at a given time, only one main current driver 21 (as shown in FIG. 2) is required for each memory block. In a typical design, four current drivers would be sufficient for each block of a MRAM cell: one for the left word line block, one for the right word line block, one for the top bit line block, and one for the bottom bit line block. A current from one such current driver 31 in FIG. 3 can be diverted to a desired row or column by appropriate current decoding block 32. Lines G30 to G3n are decoded from address and/or data-input signals. Only one of the selected lines from G30 to G3n will be high. For G30 as a selected line, G30 will be high and corresponding node 33 will be low. Low level (0 volts) at the gate of P-channel transistor M10 provides current from main current source 31 to the selected row/column line RC30.
But while FIG. 3 is a significant improvement over the previous design of FIG. 2 in reducing the number of current drivers 21, the size of transistors such as M10 has to be large so as to be able to pass large currents during MRAM write operations. There are multiple such M10 transistors, one for each row/column, therefore a large of M10 size would adversely affect die size and cost.